1. Field of the Invention
The present invention relates to a microcomputer including a memory controller that refreshes a dynamic memory.
2. Description of the Prior Art
Referring to FIGS. 7 and 8, a prior microcomputer is illustrated. In the figures, designated at 1 is a microcomputer and 2 is a dynamic random access memory (DRAM). The microcomputer 1 includes a DRAM controller 3 composed of a refresh controller (refresh control means) 3a. Designated at 4 is a central processing unit (CPU). The refresh controller 3a includes an interval counter 5 for counting an internal clock .phi., a memory control register (MCR) 6 for defining how many of the internal clock .phi. pulses should be counted, a bus priority decision circuit 7 for controlling a refresh request together with other bus requests, and a refresh address counter 8 for refreshing the DRAM2. Additionally, designated at 9 is an internal bus.
Operation of the prior microcomputer is as follows. The interval counter 5 counts the internal clock .phi. and issues a refresh request to the bus priority decision circuit 7 in a proper value of the counts defined by the MCR6 for every 32 .phi., for example from 32 .phi. to 256 .phi.. The bus priority decision circuit 7 controls the other bus requests such for example as those of a CPU bus access, a direct memory access controller (DMAC) bus access, and a bus access request by an external bus master, and updates the refresh address counter 8 to refresh the DRAM2 provided that the conditions are to respond to the refresh request. For the DRAM refreshing performed at that time RAS-only refreshing is usually available.
The prior microcomputer is constructed as described above, and the DRAM controller 3 is a refresh controller for obtaining the refresh timing, refresh address, and refresh signal for the DRAM2, without having any other function. On the contrary, in order to have an access to the DRAM2, there are required row/column address generator means for generating row/column addresses to be inputted into the DRAM2 in addition to the refresh controller 3a and access signal generator means for generating RAS and CAS signals for strobing the foregoing addresses, which are needed to be realized with an external circuit of the microcomputer shown in FIG. 8. These signals suffer from considerably severe timing thereamong, so that an external high speed TTL such as an AS (advanced Schottky) circuit, a digital delay line, and the like must be used for assuring in reserve the set-up time of a row address for the RAS signal and the holding time of the same, switching timing between row and column addresses, and the set-up and holding time of a column address for the CAS signal, etc.